Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems

Authors:
Weixun Wang;Prabhat Mishra
Affiliations:
-;-
Venue:
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Year:
2010

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System-wide leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in multitasking systems

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Energy optimization for real-time multiprocessor system-on-chip with optimal DVFS and DPM combination

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

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Abstract

System optimization techniques are widely used to improve energy efficiency as well as overall performance. Dynamic voltage scaling (DVS) is acknowledged to be successful in reducing processor energy consumption. Due to the increasing significance of the memory subsystem’s energy consumption, dynamic cache reconfiguration (DCR) techniques are recently proposed at the aim of saving cache subsystem’s energy con- sumption. As the manufacturing technology scales into the order of nanometers, leakage current, both in the processor and cache subsystem, becomes a significant contributor in the overall power dissipation. In this paper, we efficiently integrate processor voltage scaling and cache reconfiguration together that is aware of leakage power to minimize overall system energy consumption. Experimental results demonstrate that our approach outperforms existing techniques by on average 12 - 23%.