Field-programmable gate arrays
Field-programmable gate arrays
The design of an SRAM-based field-programmable gate array—part I: architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM Journal of Research and Development - Spintronics
Spin angular momentum transfer in current-perpendicular nanomagnetic junctions
IBM Journal of Research and Development - Spintronics
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Design of embedded MRAM macros for memory-in-logic applications
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Proceedings of the 37th annual international symposium on Computer architecture
Design of MRAM based logic circuits and its applications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Magnetic look-up table (MLUT) featuring radiation hardness, high performance and low power
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A resistive TCAM accelerator for data-intensive computing
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.