A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Reducing Routing Table Size Using Ternary-CAM
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Single-vDD and single-vT super-drowsy techniques for low-leakage high-performance instruction caches
Proceedings of the 2004 international symposium on Low power electronics and design
Reducing Power Consumption during TLB Lookups in a PowerPC" Embedded Processor
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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The content-based access of CAMs makes them of great interest in lookup-based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work, we present a novel banked precomputation-based architecture for low-power and storage-demanding applications where the reduction of both dynamic and leakage power consumption is addressed. Experimental results show that the proposed banked architecture reduces up to an 89% of dynamic power consumption during the search process while the leakage power consumption is also minimized up to a 91%.