Reducing TLB power requirements
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A Low-Power CAM Design for LZ Data Compression
IEEE Transactions on Computers
A Banked-Promotion TLB for High Performance and Low Power
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
An Advanced Filtering TLB for Low Power Consumption
SBAC-PAD '02 Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing
FELI: HW/SW support for on-chip distributed shared memory in multicores
Euro-Par'11 Proceedings of the 17th international conference on Parallel processing - Volume Part I
| Hi-index | 0.00 |
We present a microarchitectural-level low-power translation lookaside buffer design for embedded system applications. High-performance embedded processors with small micro-TLBs frequently encounter a large number of micro-TLB misses and many types of context switches such as internal and external interrupts. Context switches flush the micro-TLBs and therefore cause a number of unified-TLB accesses for address translation.Our method presents a microarchitecture wherein the power dissipation associated with unified-TLB accesses is minimized. In addition, our technique enables large process ID register sizes which can reduce operating system software overhead. Our experiments using specINT 2000 benchmarks show that we obtain an average power savings of 36% in the content addressable memory (CAM) comparisons for these accesses.