DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)
IEEE Transactions on Nanotechnology
Computers and Electrical Engineering
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Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of ''hardware DLLs'' by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost. We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and ''rules of the game'' for subsequent development of reconfiguration schedulers and execution environments.