A 0.9V, 65nm logic-compatible embedded DRAM with 1ms data retention time and 53% less static power than a power-gated SRAM

Authors:
Ki Chul Chun;Pulkit Jain;Chris H. Kim
Affiliations:
University of Minnesota, Minneapolis, MN, USA;University of Minnesota, Minneapolis, MN, USA;University of Minnesota, Minneapolis, MN, USA
Venue:
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Year:
2009

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Abstract

A logic-compatible low power eDRAM is demonstrated in 65nm CMOS achieving a retention time of 1.25msec and a static power dissipation of 91.3µW/Mb at 0.9V, 85ºC. A boosted 3T gain cell enhances data retention time and read speed. A regulated bit-line write scheme and a read reference bias generator mitigate write disturbance issues and improve tolerance to PVT variations.