Analysis and Implementation of Practical, Cost-Effective Networks on Chips
IEEE Design & Test
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Computers and Electrical Engineering
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In this paper, a low power joint bus and error correction coding is proposed to provide reliable and energy-efficient interconnection for network-on-chip (NoC) in nano-scale technology. The proposed self-corrected “green” (low power) coding scheme is constructed by two stages, which are triplication error correction coding (ECC) stage and green bus coding stage. Triplication ECC provides a more reliable mechanism to advanced technologies. Moreover, in view of lower latency of decoder, it has rapid correction ability to reduce the physical transfer unit size of switch fabrics by self-corrected technique in bit level. The green bus coding employs more energy reduction by a joint triplication bus power model for crosstalk avoidance. In addition, the circuitry of green bus coding is more simple and effective. Based on UMC 90nm CMOS technology, the simulation results show self-corrected green coding can achieve 34.4% energy reduction with small codec overhead. This approach not only makes the NoC applications tolerant against transient malfunctions, but also realizes energy efficiency.