Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding

Authors:
Partha Pratim Pande;Amlan Ganguly;Brett Feero;Benjamin Belzer;Cristian Grecu
Affiliations:
Washington State University, USA;Washington State University, USA;Washington State University, USA;Washington State University, USA;University of British Columbia, Canada
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

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Abstract

With the ever-increasing degrees of integration, design of communication architectures for big Systems on Chip (SoCs) is a challenge. The communication requirements of these large Multi Processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. To become a viable alternative IC design methodology, the NoC paradigm must address system-level reliability issues, which are among the dominant concerns for SoC design. The basic operations of NoCs are governed by on-chip packet switched networks. On the other hand, incorporation of different coding schemes in SoC design is being investigated as a means to increase system reliability. As NoCs are built on packet-switching, it is very natural to modify the data packets by adding extra bits of coded information to protect against any transient malfunction. By incorporating joint crosstalk avoidance coding (CAC) and forward error correction (FEC) schemes in the NoC data stream we are able to enhance the system reliability and at the same time reduce communication energy.