Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Dynamic Coding Technique For Low-Power Data Bus
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Low-power bus encoding using an adaptive hybrid algorithm
Proceedings of the 43rd annual Design Automation Conference
Scheduling with multiple voltages
Integration, the VLSI Journal
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We present in this paper a CAD tool that aims at designing low-energy buses. The Graphical User Interface (GUI) we developed manages many techniques dealing with the addressed problem: simple coding, coding subject to fixed / dynamic probabilities and an enhanced dynamic probabilities-based technique. Moreover, this environment allows tuning the parameters of data encoding / decoding and is able to generate different gains by varying the size of the bus transferring the encoded data. Finally, this tool can be easily configured to integrate new coding techniques and use one of them when favorably compared against the other techniques.