Joint Equalization and Coding for On-Chip Bus Communication

Authors:
Srinivasa R. Sridhara;Naresh R. Shanbhag;Ganesh Balamurugan
Affiliations:
University of Illinois at Urbana Champaign;University of Illinois at Urbana Champaign;Intel Corporation, Hillsboro OR
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by RC delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speed-ups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-µm CMOS technology show that 1.28 脳 speed-up is achievable by equalization alone and 2.30 脳 speed-up is achievable by joint equalization and coding.