Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes

Authors:
Srinivasa R. Sridhara;Naresh R. Shanbhag
Affiliations:
University of Illinois at Urbana-Champaign;University of Illinois at Urbana-Champaign
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

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Abstract

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent cross-talk and provide error correction. In this paper, we present fundamental limits on the number of wires required to achieve joint crosstalk avoidance and error correction in on-chip buses. We propose a code construction that results in practical encoding and decoding schemes with the number of wires being within 35% of the fundamental limits. The proposed codes, when applied to a 10-mm 32-bit bus in a 0.13-µm CMOS technology with low-swing signaling, provide 2.14脳 speed-up and 27.5% energy savings without any loss in reliability.