Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Optimization of throughput performance for low-power VLSI interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel buses under different latency and power constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90-nm technology.