Switching sensitive driver circuit to combat dynamic delay in on-chip buses

Authors:
Roshan Weerasekera;Li-Rong Zheng;Dinesh Pamunuwa;Hannu Tenhunen
Affiliations:
Laboratory of Electronics and Computer Systems (LECS), KTH Microelectronics and Information Technology, Kista, Sweden;Laboratory of Electronics and Computer Systems (LECS), KTH Microelectronics and Information Technology, Kista, Sweden;Centre for Microsystems Engineering, Faculty of Applied Sciences, Lancaster University, Lancaster, UK;Laboratory of Electronics and Computer Systems (LECS), KTH Microelectronics and Information Technology, Kista, Sweden
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it's drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.