CLU reference manual
Delay evaluation with lumped linear RLC interconnect circuit models
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Transient simulation of lossy interconnect
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Propagation delay calculation for interconnection nets on printed circuit boards by reflected waves
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On the stability of moment-matching approximations in asymptotic waveform evaluation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Transient simulation of lossy coupled transmission lines
EURO-DAC '92 Proceedings of the conference on European design automation
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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This paper describes a circuit analysis program aimed at quickly solving linear interconnection circuits with inductance and coupling. It computes circuit responses to varying degrees of detail, varying from a simple Elmore delay to a good waveform estimate. Allowable circuit forms are much more flexible than for existing Elmore delay algorithms. Large networks or distributed lines can be reduced to a form of transfer function that can subsequently be analyzed much more efficiently with the waveform moment methods.