Clocking strategies and scannable latches for low power appliacations
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Double-Latch Clocking Scheme for Low-Power I.P. Cores
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Waveform coding for low-power digital filtering of speech data
IEEE Transactions on Signal Processing
Analysis and future trend of short-circuit power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two-phase resonant clocking for ultra-low-power hearing aid applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
Analog Integrated Circuits and Signal Processing
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The energy efficiency of a 0.25 μm general-purpose FIR filter design, based on two-phase clocking, versus a functionally equivalent benchmark, based on one-phase clocking, is demonstrated by means of measurements and transistor level simulations. Architectural improvements enable already a 20% energy savings of the two-phase clocking implementation. Yet, for the first time, the limitations imposed by the supply voltage (