Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits

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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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1997

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Abstract

In this paper, we review the algorithms and methodologies used for interconnect analysis in deep submicron integrated circuits. In particular, we examine the techniques that have been practically used for static timing and static noise analysis in the design of high-performance microprocessors. We also consider the technology and performance trends which are driving us toward more sophisticated algorithms and more complex analysis for interconnect.