Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers
Modern Operating Systems
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
A synchronization model for automata arrays
MIC '08 Proceedings of the 27th IASTED International Conference on Modelling, Identification and Control
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The ever-growing complexity of circuits becomes very hard to handle using common design techniques. The development of new design methods is required, in order to provide higher modularity. One solution is represented by automata arrays [1], which make use of a large number of relatively simple cells, each cell working most of the time independently and rarely communicating with the other ones. The parallel execution of tasks [2], implied by this approach, leads to new problems. One of the most important issues is the possible occurrence of the deadlock between the cells, during the synchronization operations. The present paper proposes an algorithm for the detection of deadlock during the design phase. An alternate solution, working at execution time, is also suggested for arrays with more complex cells, when it is not feasible to eliminate the risk of deadlock during the design phase.