Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
Tight bounds on the complexity of parallel sorting
IEEE Transactions on Computers
A minimum area VLSI network for O(log n) time sorting
IEEE Transactions on Computers
Sorting n Objects with a k-Sorter
IEEE Transactions on Computers
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter
IEEE Transactions on Parallel and Distributed Systems
How to Sort N Items Using a Sorting Network of Fixed I/O Size
IEEE Transactions on Parallel and Distributed Systems
Sorting on Electronic Computer Systems
Journal of the ACM (JACM)
Parallel Sorting Algorithms
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Energy-efficient single-clock-cycle binary comparator
International Journal of Circuit Theory and Applications
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The coming of multimedia era and information security era indicates that must process longer digit integer data. Previous sort researches focus on pure performance of large amount of finite fixed digit/bit number. This paper discusses on effectively solving arbitrary long digit integer sorting problem by HW/SW co-design under the Area x Time2 (AT2) price-performance constraint. The work proposes multi-level (two-level) sort architecture to attain the object: an accomplished fixed-digit (k-bit) hardware sorter implements the first or basic level sorting, software programmed radix 2k sort implements the second or higher level sorting. By Super Radix Sorting HW/SW co-design and reuse techniques, the work makes fixed-digit HW sorters more flexible and useful.