Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem
Communications of the ACM
A VLSI priority packet queue with inheritance and overwrite
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Providing Quality of Service Packet Switched Networks
Performance Evaluation of Computer and Communication Systems, Joint Tutorial Papers of Performance '93 and Sigmetrics '93
Design of a generalized priority queue manager for ATM switches
IEEE Journal on Selected Areas in Communications
A novel architecture for queue management in the ATM network
IEEE Journal on Selected Areas in Communications
Performance improvement of dynamic buffered ATM switch
Computers and Electrical Engineering
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Applications with real-time traffic, such as video and voice, require quality-of-service (QoS) guarantees, such as bounded end-to-end delays and bounded cell loss probabilities. In order to provide the QoS guarantees for each connection in ATM networks, link scheduling to prioritize the transmission of queued cells is desirable. A hardware priority queue is then necessary since fast cell switching is hard to be realized in software. In addition, the queue has to be scalable with respect to the number of cells and the number of priority levels. A failure in the priority queue, however, will jeopardize the QoS guarantees for time-critical cells. Moreover, the errors occurred in the queue are unlikely to be detected at the destination. In this paper, we present a fast and scalable priority queue architecture for ATM switches. The queue can reconfigure itself once an error is detected, and thus it will continue normal operation even in the event of a failure.