Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
Design and Analysis of High Performance Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of an input/output buffered-type ATM LAN switch with back-pressure function
IEEE/ACM Transactions on Networking (TON)
Dynamic queue length thresholds for shared-memory packet switches
IEEE/ACM Transactions on Networking (TON)
Effect of windowing policies for input buffered ATM switch
Computer Networks and ISDN Systems
Optimal buffer management policies for shared-buffer ATM switches
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Evaluation of pipelined dilated banyan switch architectures for ATM networks
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Dynamic buffer allocation in an ATM switch
Computer Networks: The International Journal of Computer and Telecommunications Networking
Simulation of dynamic input buffer space in multistage interconnection networks
Advances in Engineering Software
Design and analysis of the stacked-Banyan ATM switch fabric
Computer Networks: The International Journal of Computer and Telecommunications Networking
Multicast performance in shared-memory ATM switches
Performance Evaluation
Performance comparison criteria for ATM switch models
Computer Networks: The International Journal of Computer and Telecommunications Networking - Special Issue: performance modeling and evaluation of ATM networks
A switched priority scheduling mechanism for ATM switches with multi-class output buffers
Computer Networks: The International Journal of Computer and Telecommunications Networking
Finite Buffer Analysis of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance analysis of finite buffer discrete-time queue with bulk service
Computers and Operations Research
Directed virtual path layouts in ATM networks
Theoretical Computer Science - Special issue: Distributed computing
A new shared-buffer packet switch in ATM networks
Computer Communications
A scalable and reconfigurable priority queue architecture for ATM switches
Computer Communications
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Performance of ATM networks depends on switch performance and architecture. This paper presents a simulation study of a new dynamic allocation of input buffer space in ATM switching elements. The switching elements are composed of input and output buffers which are used to store received and forwarded cells, respectively. Efficient and fair use of buffer space in an ATM switch is essential to gain high throughput and low cell loss performance from the network. In this paper, input buffer space of each switching element is allocated dynamically as a function of traffic load. A shared buffer pool is provided with threshold-based virtual partition among input ports, which supplies the necessary input buffer space as required by each input port. The system behaviour under varying traffic loads has investigated using a simulation program. Also, a comparison with a static allocation scheme shows that the threshold based dynamic buffer allocation scheme ensures an increased network throughput and a fair share of the buffer space even under bursty loading conditions.