Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
MVAMIN: mean value analysis algorithms for multistage interconnection networks
Journal of Parallel and Distributed Computing
Performance analysis of finite buffered multistage interconnection networks
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
On Multistage Interconnection Networks with Small Clock Cycles
IEEE Transactions on Parallel and Distributed Systems
Congested Banyan network analysis using congested-queue states and neighboring-queue effects
IEEE/ACM Transactions on Networking (TON)
Design and Analysis of High Performance Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of Switch-Based Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Architecture Scalability of Parallel Vector Computers with a Shared Memory
IEEE Transactions on Computers
Analysis of Finite Buffered Multistage Combining Networks
IEEE Transactions on Parallel and Distributed Systems
Performance improvement of dynamic buffered ATM switch
Computers and Electrical Engineering
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Proposes an analysis technique for a class of Multistage Interconnection Networks (MIN's) that have finite buffers at their switch inputs and operate in a synchronous packet-switched mode. The authors examine the issue of clock period in design and analysis of synchronous MIN's and propose a model based on small clock periods. Then they analyze their "small cycle" design and compare the results with those obtained from the standard "big cycle" model that is currently used. The significant performance improvement of their model is shown based on various clock width, data width, and buffer length.