Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
Proceedings of the 1st International Conference on Supercomputing
A Performance Bound of Multistage Combining Networks
IEEE Transactions on Computers
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
A performance bound analysis of multistage combining networks using a probabilistic model
ICS '91 Proceedings of the 5th international conference on Supercomputing
A Cost-Effective Combining Structure for Large-Scale Shared-Memory Multiprocessors
IEEE Transactions on Computers
On the effectiveness of combining in resolving “hot spot” contention
Journal of Parallel and Distributed Computing
Systolic combining switch designs
Systolic combining switch designs
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Finite Buffer Analysis of Multistage Interconnection Networks
IEEE Transactions on Computers
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Analyzing the performance of finite buffered multistage networks has been considered a difficult task because of dynamic blocking effects due to finite sized buffers. With the multistage networks enhanced with combining capability, in which multiple requests directed to a shared location combine together to form a single request to be forwarded, the analysis becomes even more difficult due to the interactions between combining probability and queuing delay. Performance bounds for combining networks are known under two extreme assumptions: infinite combining queues and saturated finite combining queues. We analyze multistage combining networks with the consideration of blocking due to finite combining queues. Our analysis provides iterative solutions for combining probability, blocking probability, and queuing delay.