Performance of unbuffered shuffle-exchange networks
IEEE Transactions on Computers - The MIT Press scientific computation series
Using feedback to control tree saturation in multistage interconnection networks
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Design of an integrated services packet network
SIGCOMM '85 Proceedings of the ninth symposium on Data communications
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Finite Buffer Analysis of Multistage Interconnection Networks
IEEE Transactions on Computers
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Congested Banyan network analysis using congested-queue states and neighboring-queue effects
IEEE/ACM Transactions on Networking (TON)
Architecture Scalability of Parallel Vector Computers with a Shared Memory
IEEE Transactions on Computers
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In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. Ding and Bhuyan (1994), however, have shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this short note, we present a model for estimating the performance of multibuffered MIN's employing the approach. Using the model, the relative effectiveness of the approach is identified compared to the traditional design