High-performance computer architecture
High-performance computer architecture
Distributing Hot-Spot Addressing in Large-Scale Multiprocessors
IEEE Transactions on Computers
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Modern control theory (3rd ed.)
Modern control theory (3rd ed.)
Adaptive backoff synchronization techniques
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Alleviation of tree saturation in multistage interconnection networks
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Performance analysis of finite buffered multistage interconnection networks
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Increasing network bandwidth on meshes
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Using a Multipath Network for Reducing the Effects of Hot Spots
IEEE Transactions on Parallel and Distributed Systems
On Multistage Interconnection Networks with Small Clock Cycles
IEEE Transactions on Parallel and Distributed Systems
Prevention of Congestion in Packet-Switched Multistage Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
Universal congestion control for meshes
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
NIFDY: a low overhead, high throughput network interface
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Evaluation of Two Traffic Distribution Strategies for a Dual-Network Multiprocessor System
IEEE Transactions on Parallel and Distributed Systems
Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router
Journal of Systems Architecture: the EUROMICRO Journal
The Journal of Supercomputing
Switch fabric design for high performance IP routers: a survey
Journal of Systems Architecture: the EUROMICRO Journal
Interconnection network front-end controller combining to reduce hot spots effects
Computer Communications
Channel reservation protocol for over-subscribed channels and destinations
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
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In this paper, we propose the use of feedback schemes in multiprocessors which use an interconnection network with distributed routing control. We show that by altering system behavior so as to minimize the occurrence of a performance-degrading situation in the network, the overall throughout of the system can be improved.As an example, we have considered the problem of tree saturation caused by hot spots in multistage interconnection networks. Tree saturation degrades the performance of all processors in a system, including those not participating in the hot spot activity. We see that feedback schemes can be used to control tree saturation, reduce degradation to memory requests that are not to the hot memory module and increase overall system bandwidth. As a companion to feedback schemes, damping schemes are also considered. Simulation studies presented in this paper show that feedback schemes can improve overall system performance significantly in many cases.