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IEEE Transactions on Parallel and Distributed Systems
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IEEE Transactions on Parallel and Distributed Systems
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IEEE Transactions on Parallel and Distributed Systems
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IEEE Transactions on Computers
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
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IEEE Transactions on Parallel and Distributed Systems
ICCS '02 Proceedings of the International Conference on Computational Science-Part III
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We present an analytical model for evaluating the performance of finite-buffered packet switching multistage interconnection networks using blocking switches under any general traffic pattern. Most of the previous research work has assumed unbuffered, single buffer or infinite buffer cases, and all of them assumed that every processing element had the same traffic pattern (either a uniform traffic pattern or a specific hot spot pattern). However, their models cannot be applied very generally. There is a need for an analytical model to evaluate the performance under more general conditions.We first present a description of a decomposition & iteration model which we propose for a specific hot spot pattern. This model is then extended to handle more general traffic patterns using a transformation method. For an even more general traffic condition where each processing element can have its own traffic pattern, we propose a superposition method to be used with the iteration model and the transformation method. We can extend the model to account for processing elements having different input rates by adding weighting factors in the analytical model.An approximation method is also proposed to refine the analytical model to account for the memory characteristic of a blocking switch which causes persistent blocking of packets contending for the same output ports. The analytical model is used to evaluate the uniform traffic pattern and a very general traffic pattern " EFOS". Comparison with simulation indicates that the analytical model is very accurate.