Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
The parallel graph reduction machine, Alice
Proc. of a workshop on Graph reduction
Performance modelling of parallel computer architectures
SIGMETRICS '86/PERFORMANCE '86 Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation
The Representation of Switching Networks in Queueing Models of Parallel Systems
Performance '87 Proceedings of the 12th IFIP WG 7.3 International Symposium on Computer Performance Modelling, Measurement and Evaluation
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
ALICE a multi-processor reduction machine for the parallel evaluation CF applicative languages
FPCA '81 Proceedings of the 1981 conference on Functional programming languages and computer architecture
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Traffic studies of unbuffered Delta networks
IBM Journal of Research and Development
A Cost-Effective Combining Structure for Large-Scale Shared-Memory Multiprocessors
IEEE Transactions on Computers
Prevention of Congestion in Packet-Switched Multistage Interconnection Networks
IEEE Transactions on Parallel and Distributed Systems
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A major component of a parallel machine is its interconnection network, which provides concurrent communication between the processing elements. It is common to use a multi-stage interconnection network (MIN) which is constructed using crossbar switches and introduces not only contention for destination addresses but also additional contention for internal switches. Both types of contention are increased when non-local communication across a MIN becomes concentrated on a certain destination address, for example when a frequently-accessed data structure is stored entirely in one element of a distributed memory. Such an address, often called a hot-spot, affects the blocking probability of paths to other destination addresses because of the shared internal switches. This paper describes an analytical model of hot-spot contention and quantifies its effect on the performance of a MIN with a circuit switching communication protocol. We obtain performance measures for a MIN in which partial paths are held during path building and one destination address is more frequently chosen by incoming traffic than other addresses.