A Performance Bound of Multistage Combining Networks
IEEE Transactions on Computers
Introduction to queueing theory (2nd ed)
Introduction to queueing theory (2nd ed)
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
An analytic model of multistage interconnection networks
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
A Markov chain approximation for the analysis of banyan networks
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
SIGMETRICS '91 Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems
MVAMIN: mean value analysis algorithms for multistage interconnection networks
Journal of Parallel and Distributed Computing
Performance Analysis of Multistage Interconnection Network Configurations and Operations
IEEE Transactions on Computers
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors
IEEE Transactions on Computers
Performing Permutations on Interconnection Networks by Regularly Changing Switch States
IEEE Transactions on Parallel and Distributed Systems
A new modelling approach of wormhole-switched networks with finite buffers
International Journal of Parallel, Emergent and Distributed Systems
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In this paper, we present a queueing model for performance analysis of finite-buffered multistage interconnection networks. The proposed model captures network behavior in an asynchronous communication mode and is based on realistic assumptions. A uniform traffic model is developed first and then extended to capture nonuniform traffic in the presence of hot-spot. Throughput and delay are computed using the proposed model and the results are validated via simulation. The analysis is extended to predict performance of MIN-based multiprocessors. The effects of buffer length, switch size, and the maximum allowable outstanding requests on the system performance are discussed. Various design decisions using this model are drawn with respect to delay, throughput, and system power.