High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
MVAMIN: mean value analysis algorithms for multistage interconnection networks
Journal of Parallel and Distributed Computing
Finite Buffer Analysis of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance improvement of dynamic buffered ATM switch
Computers and Electrical Engineering
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Small switching elements are the key components of multistage interconnection networks (MINs) used in multiprocessors and in high speed switching fabrics. Clock design for synchronous MINs is an important issue. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual data transfer takes place during the second part. We propose a new control design for single queue MINs that reduces the duration of the clock period by making use of output buffers and acknowledgments. The reduction in the clock period comes from the addition of two-unit output buffers, introducing a sophisticated hardware control mechanism, and sacrificing the FIFO feature. We develop an analytical model to compare its performance with the existing designs reported in the literature. We validate our model with extensive simulation studies.