Dataflow graph partitioning for optimal spatio-temporal computation on a coarse grain reconfigurable architecture

Authors:
Ratna Krishnamoorthy;Keshavan Varadarajan;Masahiro Fujita;Mythri Alle;S. K. Nandy;Ranjani Narayan
Affiliations:
Dept. of Electronics Engineering, The University of Tokyo, Tokyo, Japan;CAD Lab, SERC, Indian Institute of Science, Bangalore, India;Dept. of Electronics Engineering, The University of Tokyo, Tokyo, Japan;CAD Lab, SERC, Indian Institute of Science, Bangalore, India;CAD Lab, SERC, Indian Institute of Science, Bangalore, India;Morphing Machines, Bangalore, India
Venue:
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Year:
2011

Citing 6
Cited 0

Efficient network flow based min-cut balanced partitioning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers

IEEE Transactions on Computers
Reconfigurable computing: what, why, and implications for design automation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A decade of reconfigurable computing: a visionary retrospective

Proceedings of the conference on Design, automation and test in Europe
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
REDEFINE: Runtime reconfigurable polymorphic ASIC

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Coarse Grain Reconfigurable Architectures(CGRA) support Spatial and Temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. We extend Edge-Betweenness Centrality scheme, originally used for detecting community structures in social and biological networks, for partitioning instructions of a dataflow graph. Comparisons of execution time for several applications run on a simulator for REDEFINE, a CGRA proposed in literature, indicate that Centrality scheme outperforms several other schemes with 2-18% execution time speedup.