Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

Authors:
Mythri Alle;Keshavan Varadarajan;Alexander Fell;S. K. Nandy;Ranjani Narayan
Affiliations:
CAD Lab, Indian Institute Of Science, Bangalore,;CAD Lab, Indian Institute Of Science, Bangalore,;CAD Lab, Indian Institute Of Science, Bangalore,;CAD Lab, Indian Institute Of Science, Bangalore,;Morphing Machines Pvt. Ltd, Bangalore,
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

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Abstract

In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.