The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
A scalable dataflow structure store
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Resource management in a multi-ring dataflow machine
Proceedings of the conference on CONPAR 88
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Control of parallelism in the Manchester Dataflow Machine
Proceedings of the Functional Programming Languages and Computer Architecture
A hardware simulator for a multi-ring dataflow machine
A hardware simulator for a multi-ring dataflow machine
Manchester data-flow: a progress report
ICS '92 Proceedings of the 6th international conference on Supercomputing
A model for dataflow based vector execution
ICS '94 Proceedings of the 8th international conference on Supercomputing
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Asynchrony in parallel computing: from dataflow to multithreading
Progress in computer research
Iterative Instructions in the Manchester Dataflow Computer
IEEE Transactions on Parallel and Distributed Systems
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
REDEFINE: Runtime reconfigurable polymorphic ASIC
ACM Transactions on Embedded Computing Systems (TECS)
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
WSEAS Transactions on Computers
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The Present Manchester Dataflow Machine is constructed using standard TTL technology and is not designed with raw processing power in mind. This paper discusses the issues raised in the redesign of the machine using supercomputer technology. The resulting machine structure is presented in some detail, together with the initial results of simulation which indicate that a performance of hundreds of megaflops appears readily achievable.