The Manchester prototype dataflow computer
Communications of the ACM - Special section on computer architecture
Evaluation of a prototype data flow processor of the SIGMA-1 for scientific computations
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
Code Optimization for Tagged-Token Dataflow Machines
IEEE Transactions on Computers
The Epsilon dataflow processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The price of asynchronous parallelism: an analysis of dataflow architectures
Proceedings of the conference on CONPAR 88
Resource management in a multi-ring dataflow machine
Proceedings of the conference on CONPAR 88
The specification of a new Manchester Dataflow machine
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Control of parallelism in the Manchester Dataflow Machine
Proceedings of the Functional Programming Languages and Computer Architecture
Graph transformation algorithms for array memory optimization in applicative languages
Graph transformation algorithms for array memory optimization in applicative languages
A quantitative analysis of locality in dataflow programs
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
An analysis of loop latency in dataflow execution
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Manchester data-flow: a progress report
ICS '92 Proceedings of the 6th international conference on Supercomputing
Generation and quantitative evaluation of dataflow clusters
FPCA '93 Proceedings of the conference on Functional programming languages and computer architecture
A model for dataflow based vector execution
ICS '94 Proceedings of the 8th international conference on Supercomputing
An evaluation of bottom-up and top-down thread generation techniques
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
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The authors investigate the nature and extent of the benefits and adverse effects of iterative instructions in the prototype Manchester Dataflow Computer. Iterative instructions are shown to be highly beneficial in terms of the number of instructions executed and the number of tokens transferred between modules during a program run. This benefit is apparent at hardware level, giving significantly reduced program execution times. However, the full benefits are not realized due to interference between lengthy iterative instructions. It is suggested that restructuring of buffers and the function unit array in the prototype hardware configuration can reduce this interference. Other possibilities for improvement are suggested. For example, the slowdown effect observed in hardware speedup curves could be tackled by treating iterative instructions differently from fine-grain instructions. An alternative structure for the processing element in which certain function units are specialized for executing iterative instructions is being investigated in this connection.