The specification of a new Manchester Dataflow machine
ICS '89 Proceedings of the 3rd international conference on Supercomputing
IEEE Transactions on Parallel and Distributed Systems
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
Synthesis of application accelerators on Runtime Reconfigurable Hardware
ASAP '08 Proceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors
REDEFINE: Runtime reconfigurable polymorphic ASIC
ACM Transactions on Embedded Computing Systems (TECS)
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
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In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.