Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The Garp Architecture and C Compiler
Computer
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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In this paper, a temporal partitioning algorithm is presented which partitions data flow graphs in a real-time domain. Timing constraint is a critical factor in temporal partitioning of real-time reconfigurable design. An incremental algorithm is presented to partition data flow graphs while meeting the timing constraints by obtaining the target number of partitions. In addition, the proposed algorithm attempts to minimize the logic resources used for implementing the real-time application. In this algorithm, selecting the appropriate nodes and moving them between subsequent partitions results in more area balanced partitions and less number of partitions.