COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the 6th international workshop on Hardware/software codesign
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
IEEE Transactions on Computers
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FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
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CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Polynomial-time subgraph enumeration for automated instruction set extension
Proceedings of the conference on Design, automation and test in Europe
Instruction-set customization for real-time embedded systems
Proceedings of the conference on Design, automation and test in Europe
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
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SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Shared reconfigurable fabric for multi-core customization
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MORP: makespan optimization for processors with an embedded reconfigurable fabric
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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This paper explores runtime reconfiguration of custom instructions in the context of multi-tasking real-time embedded systems. We propose a pseudo-polynomial time algorithm that minimizes processor utilization through customization and runtime reconfiguration, while satisfying all the timing constraints. Our experimental infrastructure consists of Stretch customizable processor supporting runtime reconfiguration as the hardware platform and realistic embedded benchmarks as applications. We observe that runtime reconfiguration of custom instructions can help to reduce the processor utilization by up to 64%. The experimental results also demonstrate that our algorithm is highly scalable and achieves optimal or near optimal (3% difference) processor utilization.