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Discrete Applied Mathematics - Special volume: first international colloquium on graphs and optimization (GOI), 1992
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ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
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Code transformation strategies for extensible embedded processors
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Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the conference on Design, automation and test in Europe
Optimizing instruction-set extensible processors under data bandwidth constraints
Proceedings of the conference on Design, automation and test in Europe
Polynomial-time subgraph enumeration for automated instruction set extension
Proceedings of the conference on Design, automation and test in Europe
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The Instruction-Set Extension Problem: A Survey
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Speculative DMA for architecturally visible storage in instruction set extensions
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Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Note: On the number of connected convex subgraphs of a connected acyclic digraph
Discrete Applied Mathematics
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Fast enumeration of maximal valid subgraphs for custom-instruction identification
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Evaluating design trade-offs in customizable processors
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Design-space exploration of resource-sharing solutions for custom instruction set extensions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Algorithms for the automatic extension of an instruction-set
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Runtime reconfiguration of custom instructions for real-time embedded systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An efficient algorithm for custom instruction enumeration
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Exact custom instruction enumeration for extensible processors
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A just-in-time customizable processor
Proceedings of the International Conference on Computer-Aided Design
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Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automatically select the optimal set of custom instructions. Therefore, heuristic techniques are often employed to quickly search the design space. In this paper, we present an efficient algorithm for exact enumeration of all possible candidate instructions given the dataflow graph (DFG) corresponding to a code fragment. Even though this is similar to the "subgraph enumeration" problem (which is exponential), we find that most subgraphs are not feasible candidates for various reasons. In fact, the number of candidates is quite small compared to the size of the DFG. Compared to previous approaches, our technique achieves orders of magnitude speedup in enumerating these candidate custom instructions for very large DFGs.