Experiments with a Program Timing Tool Based on Source-Level Timing Schema
Computer - Special issue on real-time systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Developing Real-Time Tasks With Predictable Timing
IEEE Software
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Custom-instruction synthesis for extensible-processor platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Instruction-set customization for real-time embedded systems
Proceedings of the conference on Design, automation and test in Europe
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Energy-aware instruction-set customization for real-time embedded multiprocessor systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Evaluating design trade-offs in customizable processors
Proceedings of the 46th Annual Design Automation Conference
Algorithms for generating convex sets in acyclic digraphs
Journal of Discrete Algorithms
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Instruction set extension generation with considering physical constraints
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Epipe: A low-cost fault-tolerance technique considering WCET constraints
Journal of Systems Architecture: the EUROMICRO Journal
Hi-index | 0.00 |
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).