A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)

Authors:
Kingshuk Karuri;Rainer Leupers;Gerd Ascheid;Heinrich Meyr
Affiliations:
Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany;Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany;Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany;Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany
Venue:
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Year:
2009

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Abstract

Instruction-Set Extensions (ISEs) have gained prominence in the past few years as a useful method for tailoring the ISAs (Instruction-Set Architectures) of ASIPs (Application Specific Instruction-Set Processors) to the computational requirements of various embedded applications. This work presents a generic and easily adaptable flow for application oriented ISE design that supports both of the prevalent ASIP design paradigms - complete ISA design from scratch through an extensive design-space exploration, or limited ISA adaptation for a pre-designed and pre-verified base-processor core. The broad applicability of this design flow is demonstrated using ISA customization case studies for both of these two design philosophies.