Computer aids for VLSI design
Clustering and linear placement
25 years of DAC Papers on Twenty-five years of electronic design automation
Multiple-Way Network Partitioning
IEEE Transactions on Computers
Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A heuristic algorithm for small separators in arbitrary graphs
SIAM Journal on Computing
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
A branch-and-bound algorithm for the two-dimensional vector packing problem
Computers and Operations Research
Efficient network flow based min-cut balanced partitioning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A general framework for vertex orderings, with applications to netlist clustering
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multiway netlist partitioning onto FPGA-based board architecture
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Creating hierarchy in HDL-based high density FGPA design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Performance-driven partitioning using retiming and replication
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
System Partitioning of MCMs for Low Power
IEEE Design & Test
Architecture driven k-way partitioning for multichip modules
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Min-cut replication in partitioned networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Local ratio cut and set covering partitioning for huge logic emulation systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchy-driven FPGA partitioning method
DAC '97 Proceedings of the 34th annual Design Automation Conference
Architecture driven partitioning
Proceedings of the conference on Design, automation and test in Europe
Design hierarchy guided multilevel circuit partitioning
Proceedings of the 2002 international symposium on Physical design
The management of applications for reconfigurable computing using an operating system
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Place and route for massively parallel hardware-accelerated functional verification
Proceedings of the International Conference on Computer-Aided Design
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Partitioning of digital circuits has become a key problem area during the last five years. Benefits from new technologies like Multi-Chip-Modules or logic emulation strongly depend on partitioning results. Most published approaches are based on abstract graph models constructed from flat netlists, which consider only connectivity information. The approach presented in this paper uses information on design hierarchy in order to improve partitioning results and reduce problem complexity. Designs up to 150k gates have been successfully partitioned by descending and ascending the hierarchy. Compared to a standard k-way iterative improvement partitioning approach results are improved by up to 65% and runtimes are decreased by up to 99%.