Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Architecture driven circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Solving Graph Optimization Problems with ZBDDs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
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Given a system represented at gate level, we propose an algorithm mapping the design into the minimum number of FPGA's for logic emulation. We first devise a Local Ratio-cut clustering scheme to reduce the circuit complexity. Then a Set Covering partitioning approach, utilizing the paradigm of Espresso II, is proposed as an alternative to the widely adopted recursive partitioning paradigm. Experimental results have shown that our approach achieved significant improvement with much shorter run times compared to the recursive Fiduccia-Mattheyses approach on large designs. For instance, on a benchmark of 160 K gates and 90 K nets, we reduced the number of FPGA's required and the run time by 41 and 86%, respectively