Placement and routing for a field programmable multi-chip module
DAC '94 Proceedings of the 31st annual Design Automation Conference
New algorithms for min-cut replication in partitioned circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning of VLSI circuits and systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Minimum replication min-cut partitioning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Replication for logic bipartitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Network flow based multi-way partitioning with area and pin constraints
Proceedings of the 1997 international symposium on Physical design
Performance-driven multi-FPGA partitioning using functional clustering and replication
DAC '98 Proceedings of the 35th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Procedure cloning: a transformation for improved system-level functional partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance driven multi-level and multiway partitioning with retiming
Proceedings of the 37th Annual Design Automation Conference
Cell replication and redundancy elimination during placement for cycle time optimization
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 international symposium on Physical design
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Proceedings of the 2002 international symposium on Physical design
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
SAT-based optimal hypergraph partitioning with replication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Latency-optimal walks in replicated and partitioned graphs
DASFAA'11 Proceedings of the 16th international conference on Database systems for advanced applications
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Logic replication has been shown empirically to reduce pin count and partition size in partitioned networks. This paper presents the first theoretical treatment of the min-cut replication problem, which is to determine replicated logic that minimizes cut size. A polynomial time algorithm for determining min-cut replication sets for k-partitioned graphs is derived by reducing replication to the problem of finding a maximum flow. The algorithm is extended to hypergraphs and replication heuristics are proposed for the NP-hard problem with size constraints on partition components. These heuristics, which reduce the worst-case running time by a factor of O(k2) over previous methods, are applied to designs that have been partitioned into multiple FPGA's. Experimental results demonstrate that min-cut replication provides substantial reductions in the numbers of FPGA's and pins required