Quadratic Boolean programming for performance-driven system partitioning
DAC '93 Proceedings of the 30th international Design Automation Conference
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A Low Power Architecture for HASM Motion Tracking
Journal of VLSI Signal Processing Systems
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Low power design of large systems has traditionally relied on heuristics at the architectural, circuit and device levels to reduce the power dissipation. A systematic approach that efficiently partitions an MCM-based system for low power together with area, yield, reuse of cell libraries, and routing constraints has received little attention, largely because of its computational complexity and the lack of efficient optimization algorithms. This paper proposes a new four phase algorithm for system partitioning of MCMs under low power constraints, that is suitable for implementation with an integrated system prototyping environment. These algorithms utilize commercially available mixed integer programming software. This paper presents these models, explains our solutions via a simple example, and lists results of partitioning of large circuits for low power applications.