Discrete-time signal processing
Discrete-time signal processing
Image sequence analysis for three-dimensional perception of dynamic scenes
Handbook of pattern recognition and image processing (vol. 2)
Graphical Models and Image Processing
Digital Image Warping
Beyond Photography: The Digital Darkroom
Beyond Photography: The Digital Darkroom
System Partitioning of MCMs for Low Power
IEEE Design & Test
2-D Mesh Geometry and Motion Compression for Efficient Object-Based Video Representation
ICIP '97 Proceedings of the 1997 International Conference on Image Processing (ICIP '97) 3-Volume Set-Volume 3 - Volume 3
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
MPEG and multimedia communications
IEEE Transactions on Circuits and Systems for Video Technology
Evaluation of mesh-based motion estimation in H.263-like coders
IEEE Transactions on Circuits and Systems for Video Technology
New kernels for fast mesh-based motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Algorithm-based low-power VLSI architecture for 2D mesh video-object motion tracking
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.