Multiple-Way Network Partitioning
IEEE Transactions on Computers
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Spectral K-way ratio-cut partitioning and clustering
DAC '93 Proceedings of the 30th international Design Automation Conference
Partitioning very large circuits using analytical placement techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Multi-way partitioning via spacefilling curves and dynamic programming
DAC '94 Proceedings of the 31st annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A new approach for partitioning VLSI circuits on transistor level
Proceedings of the eleventh workshop on Parallel and distributed simulation
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A new k-way partitioning approach for multichip modules (MCM) is described. We apply an analytical technique combined with a problem-specific multi-way ratio cut method. Our method considers fired MCM pad positions on the substrate border and assigns the cells to regularly arranged chips on the substrate. For the first time, k-way partitioning results of benchmark circuits with up to 100,000 cells are presented. They show an excellent solution quality in terms of cut nets as well as a low maximum and average number of required chip-level pads for each chip. The average improvement of the number of cut nets compared to a recently published eigenvector-tabu-search approach is about 25%.