A new approach for partitioning VLSI circuits on transistor level

Authors:
Norbert Fröhlich;Rolf Schlagenhaft;Josef Fleischmann
Affiliations:
Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany;Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany;Institute of Electronic Design Automation, Technical University of Munich, 80290 Munich, Germany
Venue:
Proceedings of the eleventh workshop on Parallel and distributed simulation
Year:
1997

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Abstract

For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.