Circuit partitioning for waveform relaxation

Authors:
W. John;W. Rissiek;K. L. Paap
Affiliations:
Cadlab - Joint Venture University of Paderborn / Siemens Nixdorf Information Systems Bahnhofstraße 32-D-4709 Paderborn - Germany;Cadlab - Joint Venture University of Paderborn / Siemens Nixdorf Information Systems Bahnhofstraße 32-D-4709 Paderborn - Germany;GMD - Schloß Birlinghoven - St. Augustin - Germany
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

Citing 1
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A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation

EURO-DAC '92 Proceedings of the conference on European design automation
Generalized coupling as a way to improve the convergence in relaxation-based solvers

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A new approach for partitioning VLSI circuits on transistor level

Proceedings of the eleventh workshop on Parallel and distributed simulation
A new partitioning method for parallel simulation of VLSI circuits on transistor level

DATE '00 Proceedings of the conference on Design, automation and test in Europe

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Abstract

In this paper new partitioning strategies for the simulation of bipolar circuits using the waveform relaxation method are presented. On the one hand concepts known from layout-generation and node tearing simulation are used. On the other hand the hierarchical structure of the circuit description list and a minimal-cut criterion is used to find a good partitioning.With the help of these new partitioning algorithms it is possible for the first time to simulate large bipolar circuits using waveform relaxation. The applicability of the algorithms is demonstrated by the simulation of real-life circuits.