A hierarchy-driven FPGA partitioning method

Authors:
Helena Krupnova;Ali Abbara;Gabrièle Saucier
Affiliations:
Institut National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 GRENOBLE Cedex, France;Institut National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 GRENOBLE Cedex France;Institut National Polytechnique de Grenoble/CSI, 46, Avenue Felix Viallet, 38031 GRENOBLE Cedex France
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

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Abstract

This paper addresses an automatic partitioning method of adesign into several FPGAs. Although the circuit partitioningmethods have recently been significantly advanced, partitioningis commonly performed at the gate netlist level. To cope withlarge designs and explore the solution space efficiently,clustering of the logic is mandatory. In this paper, the hierarchyof the design, naturally introduced by the designer, guides thepartitioning. The basic concepts are introduced in terms of"envelope" delimiting hierarchy blocks. These concepts lead toan "envelope"-based clustering and to the proposed finalhierarchy-driven partitioning. Results are given on industrialexamples on XILINX 4000 technology.