A General Hardware Design Model for Multicontext FPGAs

Authors:
Naoto Kaneko;Hideharu Amano
Affiliations:
-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 3
Cited 0

Scheduling designs into a time-multiplexed FPGA

FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Stream Computations Organized for Reconfigurable Execution (SCORE)

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a general multicontext hardware design model to promote the use of multicontext FPGAs in wide range of applications. There are two major problems to be overcome in multicontext FPGAs programming. One is the complexity of programming an application in multicontext. The design model provides the context scheduling mechanisms to free the programmers from the low-level context management. The other is the difficulty in scheduling non-algorithmic applications. Our distributed demand-driven dynamicsc heduler facilitates their implementation. We have applied the design model to a network interface controller Martini. The result supports the effectiveness of our design model.