VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically by increasing its reconfiguration frequency. Therefore, this paper presents designs of optically differential reconfigurable gate array (ODRGA) VLSIs using 0.18 μm and 0.35 μm CMOS process technologies. Although they are a type of programmable gate array, they can be reconfigured optically in nanoseconds. This paper also discusses future scaling prospects of ODRGA-VLSIs.