0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI

Authors:
Takahiro Watanabe;Minoru Watanabe
Affiliations:
Shizuoka University, Shizuoka, Japan;Shizuoka University, Shizuoka, Japan
Venue:
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
Year:
2012

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Abstract

Currently, demand for high-speed dynamic reconfiguration of a programmable device is increasing for the purpose of increasing the performance of such devices. To support the high speed dynamic reconfiguration, optially reconfigurable gate arrays (ORGAs) have been developed up to now. An ORGA consists of a holographic memory, a laser array, and an optially reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. In addition, its large bandwidth optical connection enables high speed reconfiguration. However, photodiode sensitivities of conventional ORGAs were not good. This paper therefore presents a newly fabriated 0.18πm CMOS process optially reconfigurable gate array VLSI chip with highly sensitive photociruits.